A Novel Timing, Power, and Yield Optimization Technique for Dynamic CMOS Circuits Susceptible to Process Variations

Kumar Yelamarthi

Research output: Contribution to journal › Article › peer-review

Original language	English
Journal	IEEE Transactions on Semiconductor Manufacturing
State	Submitted - 1800

Cite this

@article{3bf57891d6314df39d5b317f222b37f8,

title = "A Novel Timing, Power, and Yield Optimization Technique for Dynamic CMOS Circuits Susceptible to Process Variations",

author = "Kumar Yelamarthi",

year = "1800",

language = "English",

journal = "IEEE Transactions on Semiconductor Manufacturing",

issn = "0894-6507",

publisher = "IEEE Transactions on Semiconductor Manufacturing",

}