A path oriented in time optimization flow for mixed-static-dynamic CMOS logic

The complexity of timing optimization has been increasing rapidly in proportion to the shrinking CMOS device size, due to the increased number of channel-connected transistors in a path, and the rising magnitude of process variations. These significant challenges can be addressed through the implementation of designs with an optimal balance between static and dynamic circuits. This paper presents a process variation-aware Path Oriented IN Time (POINT) optimization flow for mixed-static-dynamic CMOS logic designs, where a design is partitioned into static and dynamic circuits based on timing critical paths. Implemented on a 64-b adder and ISCAS benchmark circuits, the POINT optimization flow demonstrated an average improvement in delay by 44% and average improvement in delay uncertainty from process variations by 37% in comparison with a state-of-the-art commercial optimization tool.