A survey on the power and robustness of FinFET SRAM

Mahmoud Darwich, Ahmed Abdelgawad, Magdy Bayoumi

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

For the last decade, SRAM has been used for high density, high performance, and ultra-low power consumption system-on-chip (SoC) and mobile applications. That has been achieved by an aggressive feature size scaling, which resulted in severe and non-Tolerant degradation in the device physical characteristics represented by the Short Channel Effect (SCE), high leakage current and robustness problems. Moreover, SRAM stability became a critical design parameter under deep-scaled feature technology. Since planar CMOS reached the limits in shrinking the device, a new promising candidate for extreme scaled CMOS devices has emerged to overcome the previous mentioned problems and enhance the device performance. Thus, FinFET SRAM comes as the alternative to substitute Si-bulk SRAM. In this survey paper, different FinFET schemes based on both device level and SRAM circuit level are addressed and compared. Also, design challenges issues for FinFET SRAM are addressed.

Original languageEnglish
Title of host publication2016 IEEE 59th International Midwest Symposium on Circuits and Systems, MWSCAS 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509009169
DOIs
StatePublished - Jul 2 2016
Event59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016 - Abu Dhabi, United Arab Emirates
Duration: Oct 16 2016Oct 19 2016

Publication series

NameMidwest Symposium on Circuits and Systems
Volume0
ISSN (Print)1548-3746

Conference

Conference59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016
Country/TerritoryUnited Arab Emirates
CityAbu Dhabi
Period10/16/1610/19/16

Keywords

  • FinFET
  • Leakage
  • Short channel effect (SCE)
  • Stability
  • Static noise margin (SNM)

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