A survey on the power and robustness of FinFET SRAM

For the last decade, SRAM has been used for high density, high performance, and ultra-low power consumption system-on-chip (SoC) and mobile applications. That has been achieved by an aggressive feature size scaling, which resulted in severe and non-Tolerant degradation in the device physical characteristics represented by the Short Channel Effect (SCE), high leakage current and robustness problems. Moreover, SRAM stability became a critical design parameter under deep-scaled feature technology. Since planar CMOS reached the limits in shrinking the device, a new promising candidate for extreme scaled CMOS devices has emerged to overcome the previous mentioned problems and enhance the device performance. Thus, FinFET SRAM comes as the alternative to substitute Si-bulk SRAM. In this survey paper, different FinFET schemes based on both device level and SRAM circuit level are addressed and compared. Also, design challenges issues for FinFET SRAM are addressed.