A timing optimization technique for nanoscale CMOS circuits susceptible to process variations

Kumar Yelamarthi, Chien In Henry Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Performance variation is one of the primary concerns in nanoscale CMOS circuits. This performance variation is worse in circuits with multiple timing paths such as those used in microprocessors. In this paper, a Process Variation-aware, Transistor (PVT) sizing algorithm is proposed, which is capable of reducing worst-case delay, delay uncertainty, and delay sensitivity to process variations in nanoscale CMOS circuits. The proposed algorithm is based on identifying the significance of timing paths in a design, and performing respective optimization for optimal design performance. Additional advantages in this algorithm include its simplicity, accuracy, independent of the transistor order, and initial sizing factors. Using 90 nm CMOS process, the proposed algorithm has demonstrated an average improvement in worst-case delay by 36.9%, delay uncertainty by 44.1%, delay sensitivity by 19.8%, and power-delay-product by 35.3% when compared to their initial performances.

Original languageEnglish
Title of host publication2011 IEEE International Instrumentation and Measurement Technology Conference, I2MTC 2011 - Proceedings
Pages109-113
Number of pages5
DOIs
StatePublished - 2011
Event2011 IEEE International Instrumentation and Measurement Technology Conference, I2MTC 2011 - Binjiang, Hangzhou, China
Duration: May 10 2011May 12 2011

Publication series

NameConference Record - IEEE Instrumentation and Measurement Technology Conference
ISSN (Print)1091-5281

Conference

Conference2011 IEEE International Instrumentation and Measurement Technology Conference, I2MTC 2011
Country/TerritoryChina
CityBinjiang, Hangzhou
Period05/10/1105/12/11

Keywords

  • Transistor sizing
  • process variations
  • timing optimization

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