Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations

The complexity of timing optimization of high-performance circuits has been increasing rapidly in proportion to the shrinking CMOS device size, and rising magn¬¬¬¬¬¬itude of process variations. Addressing these significant challenges, this paper presents a timing optimization algorithm for CMOS dynamic logic, and a Path Oriented IN Time (POINT) optimization flow for mixed-static-dynamic CMOS logic, where a design is partitioned into static and dynamic circuits. Implemented on a 64-b adder and International Symposium on Circuits and Systems (ISCAS) benchmark circuits, the POINT optimization algorithm has shown an average improvement in delay by 38%, and delay uncertainty from process variations by 35% in comparison with a state-of-the-art commercial optimization tool.