Wireless Sensor Network (WSN) presents significant challenges for the application of distributed signal processing and distributed control. These systems will challenge us to apply appropriate techniques to construct capable processing units with sensing nodes considering energy constraints. Digital Signal Processing (DSP) is one of the capable processing units, but it is not commonly used in WSN because of the power constraint. The Multiply-Accumulate Unit (MAC) is the main computational kernel in DSP architectures. The MAC unit determines the power and the speed of the overall system; it always lies in the critical path. Developing high speed and low power MAC is crucial to use DSP in the future WSN. In this work, a fast and low power MAC Unit is proposed. The proposed architecture is based on examination of the critical delays and hardware complexities of merged MAC architectures to design a unit with a low critical path delay and low hardware complexity. The new architecture reduces the hardware complexity of the summation network, thus reduces the overall power. Increasing the speed of operation is achieved by feeding the bits of the accumulated operand into the summation tree before the final adder instead of going through the entire summation network. The ASIC implementation of the proposed 32-bit MAC unit saves 5.5% of the area, 9% of the energy, and reduces the delay by 13% compared to the regular merged MAC unit.