Fab level simulation is often used to evaluate the performance of control policies, capacity changes, mix/volume changes and design decisions in semiconductor wafer manufacture. As cluster and multi-cluster tools, such as the linked photolithography tool, are of increasing prominence in semiconductor wafer manufacture, it is important to have expressive and efficient models of these tools for use in fab-level simulation. Existing models are either too detailed for practical use or do not include key features such as the nonlinearity of tool cycle time as a function of the number of wafers per lot. To address these issues, we develop theory for the wafer exit time from a flow line with parallel servers at each process and extend it for practical application. We use the max-plus algebra to obtain an upper bound for the wafer completion times which requires less computation than full flow line simulation. We conjecture that the bound is exact; all cases studied show this to be true. Our conjectured exit time expression is independent of the order of the servers. We use our expression to develop equipment models for fab level simulation. We conduct numerical experiments that show the models are computationally efficient.