Performance optimization of dynamic CMOS circuits through transistor sizing

Kumar Yelamarthi

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

One of the predominately used circuit styles in high-performance VLSI systems is dynamic CMOS due to its advantage in speed. However, the rising magnitude of circuits implemented on a chip, along with shrinking device size and process variations have increased the complexity of implementing dynamic CMOS circuit efficiently. Answering this challenge, this paper proposes a performance optimization technique for dynamic CMOS circuits that operates based on a Schmitt Trigger and pseudo pMOS feedback keeper. When implemented using IBM 90nm CMOS process, the proposed optimization technique has shown an improvement in worst-case delay by 44.84%, delay uncertainty by 55%, delay sensitivity by 34%, and power consumption by 36% when compared to their initial performances.

Original languageEnglish
Title of host publicationIEEE CONECCT 2014 - 2014 IEEE International Conference on Electronics, Computing and Communication Technologies
PublisherIEEE Computer Society
ISBN (Print)9781479923175
DOIs
StatePublished - 2014
Event2014 IEEE International Conference on Electronics, Computing and Communication Technologies, IEEE CONECCT 2014 - Bangalore, India
Duration: Jan 6 2014Jan 7 2014

Publication series

NameIEEE CONECCT 2014 - 2014 IEEE International Conference on Electronics, Computing and Communication Technologies

Conference

Conference2014 IEEE International Conference on Electronics, Computing and Communication Technologies, IEEE CONECCT 2014
Country/TerritoryIndia
CityBangalore
Period01/6/1401/7/14

Keywords

  • low-power
  • process variations
  • timing optimization
  • transistor sizing

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