Performance Optimization of Dynamic CMOS Circuits through Transistor Sizing

Kumar Yelamarthi

Performance Optimization of Dynamic CMOS Circuits through Transistor Sizing

Kumar Yelamarthi

Engineering & Technology, School Of

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Original language	English
Title of host publication	IEEE International Conference on Electronics Computing and Communication Technologies
Publisher	2014 IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, COMPUTING AND COMMUNICATION TECHNOLOGIES (IEEE CONECCT)
ISBN (Print)	2334-0940
State	Published - 2014

Cite this

@inproceedings{748c5ae02a164477a32e57ac002b477e,

title = "Performance Optimization of Dynamic CMOS Circuits through Transistor Sizing",

author = "Kumar Yelamarthi",

year = "2014",

language = "English",

isbn = "2334-0940",

booktitle = "IEEE International Conference on Electronics Computing and Communication Technologies",

publisher = "2014 IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, COMPUTING AND COMMUNICATION TECHNOLOGIES (IEEE CONECCT)",

}

Performance Optimization of Dynamic CMOS Circuits through Transistor Sizing. / Yelamarthi, Kumar.

IEEE International Conference on Electronics Computing and Communication Technologies. 2014 IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, COMPUTING AND COMMUNICATION TECHNOLOGIES (IEEE CONECCT), 2014.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Performance Optimization of Dynamic CMOS Circuits through Transistor Sizing

AU - Yelamarthi, Kumar

PY - 2014

Y1 - 2014

M3 - Conference contribution

SN - 2334-0940

BT - IEEE International Conference on Electronics Computing and Communication Technologies

PB - 2014 IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, COMPUTING AND COMMUNICATION TECHNOLOGIES (IEEE CONECCT)

ER -

Performance Optimization of Dynamic CMOS Circuits through Transistor Sizing

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