Performance Optimization of Dynamic CMOS Circuits through Transistor Sizing

Kumar Yelamarthi

Performance Optimization of Dynamic CMOS Circuits through Transistor Sizing

Kumar Yelamarthi

Engineering & Technology, School Of

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Original language	English
Title of host publication	Performance Optimization of Dynamic CMOS Circuits through Transistor Sizing
Publisher	IEEE International Conference on Electronics, Computing, and Communication Technologies
Volume	2014
State	Published - Jan 2014

Cite this

@inproceedings{6a31d51188424ae98b53bcff6eaf93e8,

title = "Performance Optimization of Dynamic CMOS Circuits through Transistor Sizing",

author = "Kumar Yelamarthi",

year = "2014",

month = jan,

language = "English",

volume = "2014",

booktitle = "Performance Optimization of Dynamic CMOS Circuits through Transistor Sizing",

publisher = "IEEE International Conference on Electronics, Computing, and Communication Technologies",

}

Performance Optimization of Dynamic CMOS Circuits through Transistor Sizing. / Yelamarthi, Kumar.

Performance Optimization of Dynamic CMOS Circuits through Transistor Sizing. Vol. 2014 IEEE International Conference on Electronics, Computing, and Communication Technologies, 2014.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Performance Optimization of Dynamic CMOS Circuits through Transistor Sizing

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