Process variation-aware timing optimization for dynamic and mixed-static-dynamic CMOS logic

Kumar Yelamarthi, Chien In Henry Chen

Research output: Contribution to journalArticlepeer-review

5 Scopus citations

Abstract

The advancement in CMOS technology with the shrinking device size towards 32 nm has allowed for placement of billions of transistor on a single microprocessor chip. Simultaneously, it reduced the logic gate delays to the order of pico seconds. However, these low delays and shrinking device sizes have presented design engineers with two major challenges: timing optimization at high frequencies, and minimizing the vulnerability from process variations. Answering these challenges, this paper presents a process variation-aware transistor sizing algorithm for dynamic CMOS logic, and a process variation-aware timing optimization flow for mixed-static-dynamic CMOS logic. Through implementation on several benchmark circuits, the proposed transistor sizing algorithm for dynamic CMOS logic has demonstrated an average performance improvement in delay by 28%, uncertainty from process variations by 32%, while sacrificing an area of 39%. Also, through implementation on benchmark circuits and a 64-b parallel binary adder, the proposed timing optimization flow for mixed-static-dynamic CMOS logic has demonstrated a performance improvement in delay by 17% and uncertainty from process variations by 13%.

Original languageEnglish
Article number4773478
Pages (from-to)31-39
Number of pages9
JournalIEEE Transactions on Semiconductor Manufacturing
Volume22
Issue number1
DOIs
StatePublished - Feb 2009

Keywords

  • Dynamic CMOS logic
  • Mixed-static-dynamic CMOS
  • Process variations
  • Timing optimization
  • Transistor sizing

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