Process Variation-Aware Timing Optimization for Dynamic and Mixed-Static-Dynamic CMOS Logic

Kumar Yelamarthi, C-I H Chen

Research output: Contribution to journal › Article › peer-review

Original language	English
Pages (from-to)	31-39
Journal	IEEE Transactions on Semiconductor Manufacturing
Volume	22
Issue number	1
State	Published - Feb 2009

Cite this

@article{259bbe24e88d46bdb2a69a13930ba6e1,

title = "Process Variation-Aware Timing Optimization for Dynamic and Mixed-Static-Dynamic CMOS Logic",

author = "Kumar Yelamarthi and Chen, {C-I H}",

year = "2009",

month = feb,

language = "English",

volume = "22",

pages = "31--39",

journal = "IEEE Transactions on Semiconductor Manufacturing",

issn = "0894-6507",

publisher = "IEEE Transactions on Semiconductor Manufacturing",

number = "1",

}