Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic

Kumar Yelamarthi

Research output: Contribution to conferenceAbstractpeer-review

Original languageEnglish
StatePublished - Mar 18 2008
EventIEEE International Symposium on Quality Electronic Design -
Duration: Mar 18 2008Mar 18 2008

Other

OtherIEEE International Symposium on Quality Electronic Design
Period03/18/0803/18/08

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