Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic

Kumar Yelamarthi

Research output: Contribution to conference › Abstract › peer-review

Original language	English
State	Published - Mar 18 2008
Event	IEEE International Symposium on Quality Electronic Design - Duration: Mar 18 2008 → Mar 18 2008

Other	IEEE International Symposium on Quality Electronic Design
Period	03/18/08 → 03/18/08

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