Process variation aware transistor sizing for load balance of multiple paths in dynamic CMOS for timing optimization

Kumar Yelamarthi, Chien In Henry Chen

Research output: Contribution to journalArticlepeer-review

5 Scopus citations

Fingerprint

Dive into the research topics of 'Process variation aware transistor sizing for load balance of multiple paths in dynamic CMOS for timing optimization'. Together they form a unique fingerprint.

Computer Science