Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization

Kumar Yelamarthi, C-I H Chen

Research output: Contribution to journalArticlepeer-review

Abstract

invited journal
Original languageEnglish
Pages (from-to)21-28
JournalJournal of Computers, Academy Publishers
Volume3
Issue number2
StatePublished - 2008

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