Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization

Kumar Yelamarthi, C-I H Chen

Research output: Contribution to journal › Article › peer-review

Abstract

invited journal

Original language	English
Pages (from-to)	21-28
Journal	Journal of Computers, Academy Publishers
Volume	3
Issue number	2
State	Published - 2008

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title = "Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization",

abstract = "invited journal",

author = "Kumar Yelamarthi and Chen, {C-I H}",

year = "2008",

language = "English",

volume = "3",

pages = "21--28",

journal = "Journal of Computers, Academy Publishers",

publisher = "Journal of Computers, Academy Publishers",

number = "2",

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AU - Yelamarthi, Kumar

AU - Chen, C-I H

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N2 - invited journal

AB - invited journal

M3 - Article

VL - 3

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EP - 28

JO - Journal of Computers, Academy Publishers

JF - Journal of Computers, Academy Publishers

IS - 2

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