An efficient and low-power multiplication algorithm has been proposed in this chapter. It reduces the number of add operations during multiplication by rounding any sequence of 1s in the fractional part. The impact of using the proposed multiplication method on FIR and IIR filters response has been studied. Experimental results show that the proposed algorithm achieves up to 17% power saving and 16% increasing in speed, with only 1% accuracy loss compared to Horner's algorithm. The new multiplication method has been validated experimentally using the eZ430-RF2500 wireless sensor board. In the next chapter, we will study the impact of using the proposed multiplication method on the power consumption of the proposed DKF.