TY - JOUR
T1 - Timing optimization and noise tolerance for dynamic CMOS susceptible to process variations
AU - Yelamarthi, Kumar
AU - Chen, Chien In Henry
PY - 2012
Y1 - 2012
N2 - Dynamic CMOS circuits are significantly used in high-performance very large-scale integrated (VLSI) systems. However, they suffer from limitations such as noise tolerance, charge leakage, and power consumption. With the escalating impact of process variations on design performance, aggressive technology scaling, noise in dynamic CMOS circuit has become an imperative design challenge. The design performance of dynamic circuits has to be first improved for reliable operation of VLSI systems. Alongside, this impact of process variation is worse in circuits with multiple timing paths such as those used in microprocessors. In this paper, these problems of process variations, timing, noise tolerance, and power are investigated together for performance optimization. We propose a process variation-aware load-balance of multiple paths transistor sizing algorithm to: 1) improve worst-case delay, delay uncertainty, and sensitivity due to process variations in dynamic CMOS circuits, and 2) optimize dynamic CMOS circuits with MOSFET-based keepers to improve the noise tolerance. Implemented using 90-nm CMOS process, the proposed algorithm has demonstrated an average improvement in worst-case delay by 34%, delay uncertainty by 40.3%, delay sensitivity by 25.1%, and noise margins by 19.4% when compared to their initial performances.
AB - Dynamic CMOS circuits are significantly used in high-performance very large-scale integrated (VLSI) systems. However, they suffer from limitations such as noise tolerance, charge leakage, and power consumption. With the escalating impact of process variations on design performance, aggressive technology scaling, noise in dynamic CMOS circuit has become an imperative design challenge. The design performance of dynamic circuits has to be first improved for reliable operation of VLSI systems. Alongside, this impact of process variation is worse in circuits with multiple timing paths such as those used in microprocessors. In this paper, these problems of process variations, timing, noise tolerance, and power are investigated together for performance optimization. We propose a process variation-aware load-balance of multiple paths transistor sizing algorithm to: 1) improve worst-case delay, delay uncertainty, and sensitivity due to process variations in dynamic CMOS circuits, and 2) optimize dynamic CMOS circuits with MOSFET-based keepers to improve the noise tolerance. Implemented using 90-nm CMOS process, the proposed algorithm has demonstrated an average improvement in worst-case delay by 34%, delay uncertainty by 40.3%, delay sensitivity by 25.1%, and noise margins by 19.4% when compared to their initial performances.
KW - CMOS circuit
KW - delay uncertainty
KW - noise tolerance
KW - process variations
KW - timing optimization
UR - http://www.scopus.com/inward/record.url?scp=84860662302&partnerID=8YFLogxK
U2 - 10.1109/TSM.2012.2185961
DO - 10.1109/TSM.2012.2185961
M3 - Article
AN - SCOPUS:84860662302
VL - 25
SP - 255
EP - 265
JO - IEEE Transactions on Semiconductor Manufacturing
JF - IEEE Transactions on Semiconductor Manufacturing
SN - 0894-6507
IS - 2
M1 - 6140588
ER -