Timing optimization and noise tolerance for dynamic CMOS susceptible to process variations

Engineering

• Algorithm 33%
• Delay Case 33%
• Design 33%
• Electric Power Utilization 16%
• Limitations 16%
• Load Balance 16%
• Metal-Oxide-Semiconductor Field-Effect Transistor 16%
• Microprocessor Chips 16%
• Networks (Circuits) 100%
• Noise Margin 16%
• Noise Power 16%
• Noise Tolerance 66%
• Performance 50%
• Process Variation 100%
• Reliable Operation 16%
• Scaling 16%
• Transistor 33%

Computer Science

• Delay Sensitivity 16%
• Design 33%
• Design Challenge 16%
• Initial Performance 16%
• Integrated System 66%
• Load Balance 16%
• Microprocessor 16%
• Noise Margin 16%
• Performance Optimization 16%
• Power Consumption 16%
• Process Variation 100%
• Reliable Operation 16%
• Timing Optimization 16%