TY - GEN
T1 - Transistor sizing for load balance of multiple paths in dynamic CMOS for timing optimization
AU - Yelamarthi, Kumar
AU - Chen, Chien In Henry
PY - 2007
Y1 - 2007
N2 - Due to the increased importance of speed on microprocessor circuits, the complexity in transistor sizing for timing optimization increases due to channel-connected transistors on various paths of the design. In this paper, an efficient approach to transistor sizing of dynamic CMOS circuits for timing optimization while considering the Load Balance of Multiple Paths, named LBMP, is proposed. The iterative optimization algorithm is a deterministic approach and illustrated first by a 2-b weighted binary-to-thermometric converter (BTC), of which the critical path is optimized from an initial delay of 287.57 ps to an optimal delay of 161.37 ps which accounts for a 43.9% delay improvement. Then by a 64-b adder partitioned to a mixed dynamic-static style, the critical path is optimized to 686.11 ps and the power delay product is optimized to 91.6 pJ.
AB - Due to the increased importance of speed on microprocessor circuits, the complexity in transistor sizing for timing optimization increases due to channel-connected transistors on various paths of the design. In this paper, an efficient approach to transistor sizing of dynamic CMOS circuits for timing optimization while considering the Load Balance of Multiple Paths, named LBMP, is proposed. The iterative optimization algorithm is a deterministic approach and illustrated first by a 2-b weighted binary-to-thermometric converter (BTC), of which the critical path is optimized from an initial delay of 287.57 ps to an optimal delay of 161.37 ps which accounts for a 43.9% delay improvement. Then by a 64-b adder partitioned to a mixed dynamic-static style, the critical path is optimized to 686.11 ps and the power delay product is optimized to 91.6 pJ.
UR - http://www.scopus.com/inward/record.url?scp=34548133499&partnerID=8YFLogxK
U2 - 10.1109/ISQED.2007.162
DO - 10.1109/ISQED.2007.162
M3 - Conference contribution
AN - SCOPUS:34548133499
SN - 0769527957
SN - 9780769527956
T3 - Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007
SP - 426
EP - 431
BT - Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007
Y2 - 26 March 2007 through 28 March 2007
ER -