Transistor sizing for load balance of multiple paths in dynamic CMOS for timing optimization

Kumar Yelamarthi, Chien In Henry Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

Due to the increased importance of speed on microprocessor circuits, the complexity in transistor sizing for timing optimization increases due to channel-connected transistors on various paths of the design. In this paper, an efficient approach to transistor sizing of dynamic CMOS circuits for timing optimization while considering the Load Balance of Multiple Paths, named LBMP, is proposed. The iterative optimization algorithm is a deterministic approach and illustrated first by a 2-b weighted binary-to-thermometric converter (BTC), of which the critical path is optimized from an initial delay of 287.57 ps to an optimal delay of 161.37 ps which accounts for a 43.9% delay improvement. Then by a 64-b adder partitioned to a mixed dynamic-static style, the critical path is optimized to 686.11 ps and the power delay product is optimized to 91.6 pJ.

Original languageEnglish
Title of host publicationProceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007
Pages426-431
Number of pages6
DOIs
StatePublished - 2007
Event8th International Symposium on Quality Electronic Design, ISQED 2007 - San Jose, CA, United States
Duration: Mar 26 2007Mar 28 2007

Publication series

NameProceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007

Conference

Conference8th International Symposium on Quality Electronic Design, ISQED 2007
Country/TerritoryUnited States
CitySan Jose, CA
Period03/26/0703/28/07

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